1. Field of the Invention
This invention relates to detection of synchronisation data in a serial-bit digital signal, and in particular, though not exclusively, to detection of synchronisation data in serial-bit digital video signals on reproduction from a digital video tape recorder (DVTR).
2. Description of the Prior Art
Digital video signals ape recorded by DVTRs as serial-bit data streams comprising video data, error protection information, spare data capacity (which may be used fop example to record items such as dates, times and titles) and synchronisation data. The synchronisation data is crucial to recovering the video data on reproduction of the signals. The recorded serial-bit data stream is generally in the form of blocks of words which must be converted to parallel form on reproduction. The synchronisation data is required to enable identification of the first bit of each word, so as to permit deserialisation, and also to identify the first word of each block of video data words.
Usual methods of detecting, of decoding, synchronisation words are based on detection in a serial force. This is easy to implement provided the off-tape serial data Fate is slow. However, high-speed data requires the use of ECL logic. These methods then become wasteful in hardware in view of the large number of devices required.
One known method of detecting synchronisation data is disclosed in UK patent number 2089178. Here, the reproduced serial data stream is clocked at the serial data Fate through a multi-stage shift register. An output of each stage of the shift register is connected to a NAND gate which generates a pulse when the register holds the synchronisation (sync) word to be detected. Outputs of the shift register are also connected to a latch arrangement fop deserialising the data clocked through the shift register to parallel word form with arbitrary phase, i.e. the first bit of each video data word could be in any one of the bits of a parallel word. Pulses from the NAND gate are clocked through a further shift register the outputs of which are latched at the arbitrary word rate. The latch outputs are converted to binary codes which indicate the phase of the sync data relative to the parallel words produced by the latch arrangements. These codes are then used to control correct realignment of the bits of the parallel words. This system is relatively complex in terms of hardware, and is not easily adaptable to cope with longer sync codes. Furthermore, the system does not easily handle high off-tape serial data rates which in some cases can rise to over 70 MHz in shuttle replay.